• # - Serial chip types
• # - Serial chip registers
• # - Code snippets
• # - Links
• REPORT BUGS OR ERRORS IN THIS DOCUMENT

Serial chip types

• 8250 and 8250B have no scratch register
• 8250A and 16450 have the scratch register but no FIFO
• 16550 has a FIFO but it doesn't work
• 16550A has a 16-byte FIFO
• 16650 has a 32-byte FIFO, on-chip flow control, and can run up to 460800 baud (4x normal)
• 16750 has a 64-byte FIFO, on-chip flow control, and can run up to 921600 baud (8x normal). This chip is NOT pin-compatible with the others.

• They can not keep up with PC/AT I/O speed, so delays must be inserted between successive I/O instructions
• They transmit bad data when configured for 5 data bits with 1.5 stop bits
• They can occasionally drop received characters without posting a receive overrun error. This results in undetected data loss.
• They can transmit a single random character at power on

Serial chip registers

The bit rate is normally 115200 divided by the 16-bit Divisor Latch value. According to one 16550A spec sheet, 'Using a value of 0 is not recommended.'

Reading RBR (register 0) clears the Receive Data and FIFO Timeout Interrupts.

Writing THR (register 0) clears the Transmit Holding Register Empty Interrupt. If you have nothing more to transmit, reading the Interrupt ID Register (IIR) will also clear this interrupt.

Register 1: Interrupt Enable Register (IER)

The receive FIFO timeout occurs automatically, when

• there is data in the receive FIFO, but
• not enough data in the FIFO to trigger a normal Receiver Buffer Full interrupt, and
• incoming data stops for a period of 4 character times or longer.

Register 2: Interrupt ID Register (IIR; read-only)

Register 2: FIFO Control Register (FCR; write-only; 16550+)

Register 2: Enhanced FIFO control Register (EFR; write-only; 16650+)

Register 3: Line Control Register (LCR)

Register 4: Modem Control Register (MCR)

Register 5 (read-only): Line Status Register (LSR)

b7	b6	b5	b4	b3	b2	b1	b0
rfe	TEMT	THRE	BI	FE	PE	OE	DR

b7	rfe	[16550+] Receive FIFO error. Indicates that at least one byte in the receive FIFO contains a parity error, framing error, or BREAK. If the FIFOs are disabled or the chip has no FIFOs, this bit =0
b6	TEMT	Transmitter Empty. Indicates that the THR, FIFO, and transmit shift register are all empty. This bit does not generate an interrupt. If you want to use stick parity to transmit 9-bit values, you can't change the stick parity value until the transmitter is empty, so you must poll this bit. You must also disable the FIFOs to send 9-bit values.
b5	THRE	Transmitter Holding Register Empty. Set when transmitter is ready to accept a new character.
b4	BI	Break Indication. This bit is set if a BREAK is received. BREAK is a 'space' condition that lasts for at least ???
b3	FE	Framing error (invalid stop bit) in received data.
b2	PE	Parity error in received data.
b1	OE	Overrun error. New data was received before the old data in the Receiver Buffer Fegister or FIFO was read.
b0	DR	Data ready. This bit is set when a complete character has been received and transferred to the Receiver Buffer Register or FIFO. The error bits are set when the associated byte is at the top of the FIFO.

Register 6: Modem Status Register (MSR)

b7	b6	b5	b4	b3	b2	b1	b0
DCD	RI	DSR	CTS	DDCD	TERI	DDSR	DCTS

b7	DCD	Data Carrier Detect handshaking input.
b6	RI	Ring Indication handshaking input.
b5	DSR	Data Set Ready handshaking input.
b4	CTS	Clear To Send handshaking input.
b3	DDCD	Delta DCD. Set if DCD line changed state.
b2	TERI	Trailing Edge RI.
b1	DDSR	Delta DSR. Set if DSR line changed state.
b0	DCTS	Delta CTS. Set if CTS line changed state.

Register 7: Scratch Register (SCR)

You can store whatever you want in this register. It is not present, however, in 8250 and 8250B chips.

Code snippets

Simple polled serial output (good for debugging)

Links

TO DO

- info on using DMA with serial chips (b3 in FCR)
- Enhanced FIFO control Register (EFR; 16650+ chips)
- clkx4, iren, it/fc bits in reg 4 (16650/16570 chips)

REPORT BUGS OR ERRORS IN THIS DOCUMENT